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1 ISL8022 dual 2a/1.7a low quiescent current 2.25mhz high efficiency synchronous buck regulator ISL8022 the ISL8022 is a high efficiency, dual synchronous step-down dc/dc regulator that can deliver up to 2a/1.7a continuous output current per channel. the channels are 180 out-of-phase for input rms current and emi reduction.the supply voltage range of 2.8v to 5.5v allows the use of a single li+ cell, three nimh cells or a regulated 5v input. the current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the ISL8022 operates at 2.25mhz switching frequency allowing the use of small, low cost inductors and capacitors. each channel is optimized for generating an output voltage as low as 0.6v. the ISL8022 has a user configurable mode of operation-forced pwm mode and pfm/pwm mode. the forced pwm mode operation reduces noise and rf interference while the pfm mo de operation provides high efficiency by reducing switching losses at light loads. in pfm mode of operation, both channels draw a total quiescent current of only 40a hence enabling high light load efficiency in order to maximize battery life. the ISL8022 offers a 1ms power-good (pg) to monitor both outputs at power-up. when shutdown, ISL8022 discharges the outputs capacitor. other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. the ISL8022 is offered in a 4mmx3mm 12 ld dfn package with 1mm maximum height. the complete converter occupies less than 1.8cm 2 area. features ? dual 2a/1.7a high efficiency synchronous buck regulator with up to 97% efficiency, low iq (40a) ?180 out-of-phase ? start-up with pre-biased output ? selectable forced pwm mode and pfm mode ? external synchronization up to 8mhz ? negative current detection and protection ? 100% maximum duty cycle for lowest dropout ? internal current mode compensation ? peak current limiting, hiccup mode short circuit protection and over-temperature protection ? pb-free (rohs compliant) applications* (see page 17) ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ? test and measurement systems ? li-ion battery powered devices ? bar code readers related literature* (see page 17) an1554 ?ISL8022eval1z dual 2a/1.7a low quiescent current 2.25mhz high efficiency synchronous buck regulator? characteristics curve 40 50 60 70 80 90 100 0.00.20.40.60.81.01.21.41.61.82.0 e f f i c i e n c y ( % ) output load (a) 3.3v out2pfm 3.3v out2 pwm 2.5v out1pfm 2.5v out1pwm 2.25mhz 5v in at +25c caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. june 9, 2010 fn7650.0
ISL8022 2 fn7650.0 june 9, 2010 typical applications in table 1, the minimum output capacitor value is given for different output voltage to make sure the whole converter system is stable. output capacitance should increase to support faster load transient requirement. l1 1.2h lx1 pgnd fb1 vin en2 pg sync input 2.8v to 5.5v output1 2.5v/2a c1 2 x 10f ISL8022 c2 r2 316k r3 100k 22f c3 10pf l2 1.2h fb2 output2 1.8v /1.7a c4 r5 200k r6 100k 22f c5 10pf lx2 pgnd en1 figure 1. typical application diagram - dual independent outputs table 1. component value selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v c1 2x10f 2x10f 2x10f 2x10f 2x10f 2x10f c2 (or c4) 22f 22f 22f 22f 22f 22f c3 (or c5) 10pf 10pf 10pf 10pf 10pf 10pf l1 (or l2) 1.0~2.2h 1.0~2.2h 1.0~2.2h 1.5~3.3h 1.5~3.3h 1.5~4.7h r2 (or r5) 33k 100k 150k 200k 316k 450k r3 (or r6) 100k 100k 100k 100k 100k 100k
ISL8022 3 fn7650.0 june 9, 2010 block diagram lx1 + + csa1 + + ocp 1.25v 0.265v skip + + + slope comp soft start soft- start 0.6v eamp comp pwm/pfm logic controller protection driver fb1 + 0.546v pg sync shutdown pgnd oscillator bandgap scp + 0.2v en1 shutdown 1ms delay 27pf 250k 3pf 1.6k lx2 + + csa2 + + ocp 1.1v 0.265v skip + + + slope comp soft start soft- start eamp comp pwm/pfm logic controller protection driver fb2 + shutdown pgnd zero-cross sensing bandgap scp + 0.2v en2 shutdown 3pf 1.6k thermal shut down shutdown 1m vin 0.546v 0.6v vcc 27pf 250k vcc vin2 vin1 negative current limit zero-cross sensing negative current limit
ISL8022 4 fn7650.0 june 9, 2010 pin configuration ISL8022 (12 ld dfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8022irz 8022 -40 to +85 12 ld 4x3 dfn l12.4x3 ISL8022eval1z evaluation board notes: 1. add ?t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL8022 . for more information on msl please see techbrief tb363 . fb1 en1 pg vin1 lx1 fb2 en2 sync vin2 lx2 pgnd1 2 3 4 1 5 11 10 9 12 8 6 7 pgnd2 pin description pin number symbol description 1 fb1 the feedback network of the channel 1 regulator. fb1 is the negative input to the transconductance error amplifier. the output voltage is set by an ex ternal resistor divider co nnected to fb1. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and undervoltage protecti on circuitry use fb1 to monitor the channel 1 re gulator output voltage. 2 en1 regulator channel 1 enable pin. enable the output, v out1 , when driven to high. shutdown the v out1 and discharge output capacitor when driven to low. do not leave this pin floating. 3 pg 1ms timer output. at power-up or en_ hi, this output is a 1ms dela yed power-good signal for both the v out1 and v out2 voltages. there is an internal 1m pull-up resistor. 4 vin1 input supply voltage for channel 1. connect 10f ceramic capacitor to pgnd1. 5 lx1 switching node connection for channel 1. connect to one terminal of inductor for v out1 . 6 pgnd1 negative supply for power stage 1. 7 pgnd2 negative supply for powe r stage 2 and system ground. 8 lx2 switching node connection for channel 2. connect to one terminal of inductor for v out2 . 9 vin2 input supply voltage for ch 2 and to provide logic bias. make sure that v in2 is v in1 . connect 10f ceramic capacitor to pgnd2. 10 sync mode selection pin. connect to logic high or input voltage vin fo r pfm mode; connect to logic low or ground for forced pwm mode. connec t to an external function genera tor for synchronization. negative edge trigger. do not le ave this pin floating. 11 en2 regulator channel 2 enable pin. enable the output, v out2 , when driven to high. shutdown the v out2 and discharge output capacitor when driven to low. do not leave this pin floating. 12 fb2 the feedback network of the channel 2 regulator. fb2 is the negative input to the transconductance error amplifier. the output voltage is set by an ex ternal resistor divider co nnected to fb2. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and undervoltage protecti on circuitry use fb2 to monitor the channel 2 re gulator output voltage. -exposed pad the exposed pad must be connected to the sgnd pin for proper elec trical performance. add as much vias as possible for op timal thermal performance.
ISL8022 5 fn7650.0 june 9, 2010 absolute maximum ratings ( reference to gnd) thermal information supply voltage (v in ) . . . . . . -0.3v to 6v (dc) or 7v (20ms) en1, en2, pg, sync . . . . . . . . . . . . . . . -0.3v to v in + 0.3v lx1, lx2 . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 7v (20ms) fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . 3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 250v charged device model (tested per jesd22-c101e) . . . . 2k latch up (tested per jesd-78b; class 2, level a) . . . 100ma recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . 2.8v to 5.5v load current range channel 1. . . . . . . . . . . . . . . . 0a to 2a load current range channel 2. . . . . . . . . . . . . . 0a to 1.7a ambient temperature range . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 4x3 dfn package (notes 4, 5) . . 41 3 junction temperature range . . . . . . . . . . -55c to +150c storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions: t a = -40c to +85c, v in = 2.8v to 5.5v, en1 = en2 = v in , sync = 0v, l = 1.2h, c1 = 2 x 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 6) typ max (note 6) units input supply v in undervoltage lock-out threshold v uvlo rising 2.5 2.8 v falling 2.0 2.4 v quiescent supply current i vin sync = v in , en1 = en2 = v in , no switches switching 40 55 a sync = gnd, en1 = en2 = v in , f s = 2.25mhz, no load at the output 0.86 1 ma shutdown supply current i sd v in = 5.5v, en1 = en2 = gnd 6.5 12 a output regulation fb1, fb2 regulation voltage v fb_ 0.590 0.6 0.610 v fb1, fb2 bias current i fb_ vfb = 0.55v 0.1 a output voltage accuracy sync = v in , io = 0a to 2a (note 7) 1. 5 % sync = gnd, io = 0a to 2a (note 7) 1 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.8v) 0.2 %/v soft-start ramp time cycle 2ms overcurrent protection dynamic current limit on-time t ocon 17 clock pulses dynamic current limit off-time t ocoff 4ss cycle
ISL8022 6 fn7650.0 june 9, 2010 peak overcurrent limit i pk1 2.7 3.2 3.6 a i pk2 2.3 2.8 3.2 a peak skip limit i skip1 520 610 730 ma i skip2 520 610 730 ma negative current limit i valley1 -2.2 -1.6 -1 a i valley2 -2.2 -1.6 -1 a lx1, lx2 p-channel mosfet on-resistance v in = 5.5v, i o = 200ma channel 1 90 115 m v in = 5.5v, i o = 200ma channel 2 100 125 m n-channel mosfet on-resistance v in = 5.5v, i o = 200ma channel 1 80 103 m v in = 5.5v, i o = 200ma channel 2 90 112 m lx_ maximum duty cycle 100 % pwm switching frequency f s 1.8 2.25 2.7 mhz synchronization range (note 8) 5.4 8 mhz channel 1 to channel 2 phase shift ris ing edge to rising edge timing 180 lx minimum on time sync = high (forced pwm mode) 65 ns soft discharge resistance r dis_ en = low 80 100 130 pg output low voltage sinking 1ma, vfb = 0.5v 0.4 v pg pin leakage current pg = v in = 3.6v 0.01 0.1 a pg pull-up resistor 1m internal pgood low rising threshold percentage of nominal regulation voltage 85 91 97 % internal pgood low falling threshold percentage of nominal regulation voltage 78 85 92 % delay time (rising edge) 1ms internal pgood delay time (falling edge) 1 4 s en1, en2, sync logic input low 0.4 v logic input high 1.4 v sync logic input leakage current i sync pulled up to 5.5v 0.1 1 a enable logic input leakage current i en_ 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c notes: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. the operational frequency per switching cha nnel will be half of the sync frequency. 8. limits established by characterization and are not production tested. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions: t a = -40c to +85c, v in = 2.8v to 5.5v, en1 = en2 = v in , sync = 0v, l = 1.2h, c1 = 2 x 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL8022 7 fn7650.0 june 9, 2010 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. figure 2. efficiency vs load, 2.25mhz, 3.3v in pwm figure 3. efficiency vs load, 2.25mhz, 5v in pwm figure 4. efficiency vs load, 2.25mhz, 3.3v in pfm figure 5. efficiency vs load, 2.25mhz, 5v in pfm figure 6. power dissipation vs load, 2.25mhz, 1.8v, channel 2 figure 7. v out regulation vs load, 2.25mhz, 1.2v, channel1 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 2.5v out1 1.2v out1 1.5v out2 1.8v out2 40 50 60 70 80 90 100 0.00.20.40.60.81.01.21.41.61.82.0 e f f i c i e n c y ( % ) output load (a) 1.2v out1 1.5 vout1 3.3v out2 2.5v out1 1.8v out2 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 1.5v out1 2.5v out1 1.2v out1 1.8v out2 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 3.3v out2 1.2v out1 1.5v out1 2.5v out1 1.8v out2 0.00 0.15 0.30 0.45 0.60 0.75 0.90 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 p o w e r d is s ip a t io n (w ) output load (a) 5 v in pwm 3.3v in pfm 5v in pfm 3.3v in pwm 1.17 1.18 1.19 1.20 1.21 1.22 1.23 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 5v in pwm 3.3v v in pwm 3.3v v in pfm 5 v in pfm
ISL8022 8 fn7650.0 june 9, 2010 figure 8. v out regulation vs load, 2.25mhz, 1.5v channel2 figure 9. v out regulation vs load, 2.25mhz, 2.5v channel1 figure 10. v out regulation vs load, 2.25mhz, 1.8v, channel 2 figure 11. output voltage regulation vs v in 2.5v channel 1 figure 12. output voltage regulation vs v in 1.8v channel 2 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) 1.48 1.49 1.50 1.51 1.52 1.53 1.54 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e (v ) output load (a) 5v in pfm 3.3v v in pwm 5v in pwm 3.3v v in pfm 2.47 2.48 2.49 2.50 2.51 2.52 2.53 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e (v ) output load (a) 5v in pfm 3.3v v in pwm 5v in pwm 3.3v v in pfm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e (v ) output load (a) 5 v in pfm 5v in pwm 3.3v v in pfm 3.3v v in pwm 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 o u t p u t v o l t a g e ( v ) input voltage (v) 1a load 2a load 0a load pwm 0a load pfm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 o u t p u t v o l t a g e ( v ) input voltage (v) 0.8a load 1.7a load 0a load pwm 0a load pfm
ISL8022 9 fn7650.0 june 9, 2010 figure 13. steady state operation at no load channel 1 (pwm) figure 14. steady state operation at no load channel 2 (pwm) figure 15. steady state operation at no load channel 1 (pfm) figure 16. steady state operation at no load channel 2 (pfm) figure 17. steady state operation at full load channel 1 figure 18. steady state operation with full load channel 2 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) lx1 2v/div il1 0.2a/div v out1 ripple 20mv/div tb = 200ns/div lx2 2v/div il2 0.2a/div v out2 ripple 20mv/div tb = 200ns/div lx1 2v/div il1 0.5a/div v out1 ripple 20mv/div tb = 500ns/div lx2 2v/div il2 0.5a/div v out2 ripple 20mv/div tb = 500ns/div lx1 2v/div il1 1a/div v out1 ripple 20mv/div tb = 200ns/div lx2 2v/div il2 1a/div v out2 ripple 20mv/div tb = 200ns/div
ISL8022 10 fn7650.0 june 9, 2010 figure 19. load transient channel 1 (pwm) f igure 20. load transient channel 2 (pwm) figure 21. load transient channel 1 (pfm) figure 22. load transient channel 2 (pfm) figure 23. soft-start with no load channel 1 (pwm) figure 24. soft-start with no load channel 2 (pwm) typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) il1 1a/div v out1 ripple 50mv/div pg 5v/div tb = 200s/div pg 5v/div il2 1a/div v out2 ripple 50mv/div tb = 200s/div lx1 2v/div il1 1a/div v out1 ripple 50mv/div tb = 1ms/div lx2 2v/div il2 1a/div v out2 ripple 50mv/div tb = 1ms/div en1 2v/div il1 0.5a/div v out1 1v/div pg 5v/div tb = 500s/div en2 2v/div il2 0.5a/div v out2 1v/div pg 5v/div tb = 500s/div
ISL8022 11 fn7650.0 june 9, 2010 figure 25. soft-start at no load channel 1 (pfm) figure 26. soft-start at no load channel 2 (pfm) figure 27. soft-start at full load channel 1 figure 28. soft-start at full load channel 2 figure 29. soft-discharge shutdown channel 1 figure 30. soft-discharge shutdown channel 2 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) en1 2v/div il1 0.5a/div v out1 1v/div pg 5v/div tb = 500s/div en2 2v/div il2 0.5a/div v out2 1v/div pg 5v/div tb = 500s/div en1 2v/div il1 1a/div v out1 1v/div pg 5v/div tb = 500s/div en2 2v/div il2 1a/div v out2 1v/div pg 5v/div tb = 500s/div en1 2v/div il1 0.2a/div v out1 1v/div pg 5v/div tb = 200s/div en2 2v/div il2 0.2a/div v out2 1v/div pg 5v/div tb = 200s/div
ISL8022 12 fn7650.0 june 9, 2010 figure 31. steady state operation at no load (pfm) with frequency = 8mhz channel 1 figure 32. steady state operation at no load (pfm) with frequency = 8mhz channel 2 figure 33. steady state operation at full load (pfm) with frequency = 8mhz channel 1 figure 34. steady state operation at full load (pfm) with frequency = 8mhz channel 2 figure 35. vout1 hard short to vin negative current waveforms at high line channel 1 figure 36. recovery from hard short negative current waveforms v out1 channel 1 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) synch 2v/div lx1 2v/div il1 0.2a/div v out1 ripple 20mv/div tb = 100ns/div synch 2v/div lx2 2v/div il2 0.2a/div v out2 ripple 20mv/div tb = 100ns/div synch 2v/div lx1 2v/div il1 1a/div v out1 ripple 20mv/div tb = 100ns/div synch 2v/div lx2 2v/div il2 0.5a/div v out2 ripple 20mv/div tb = 100ns/div pg 1v/div lx1 2v/div il1 0.5a/div v out1 2v/div tb = 1s/div pg 1v/div lx1 2v/div il1 0.5a/div v out1 2v/div tb = 1s/div
ISL8022 13 fn7650.0 june 9, 2010 figure 37. vout2 hard short to vin negative current waveforms at high line channel 2 figure 38. recovery from hard short negative current waveforms v out2 channel 2 figure 39. output short circuit channel 1 figure 40. output short circuit recovery channel 1 figure 41. output short circuit channel 2 figure 42. output short circuit recovery channel 2 typical operating performance (unless otherwise noted) operating conditions are: t a =+25c, v vin = 2.8v to 5.5v, en = v in , l1 = l2 = 1.2h, c1 = 10f, c2 = c4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) pg 1v/div lx2 2v/div il2 0.5a/div v out2 2v/div tb = 10s/div pg 1v/div lx2 2v/div il2 0.5a/div v out2 2v/div tb = 1s/div lx1 5v/div il1 2a/div v out1 2v/div pg 5v/div tb = 5s/div lx1 5v/div il1 2a/div v out1 2v/div pg 5v/div tb = 1ms/div lx2 5v/div il2 2a/div v out2 1v/div pg 5v/div tb = 5s/div lx2 5v/div il2 2a/div v out2 1v/div pg 5v/div tb = 1ms/div
ISL8022 14 fn7650.0 june 9, 2010 theory of operation the ISL8022 is a dual 2a/1.7a step-down switching regulator optimized for battery-powered or mobile applications. the regulator operates at 2.25mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the two channels are 180 out-of-phase operation. the quiescent current when the outputs are not loaded is typically only 40a. the supply current is typically only 6.5a when the regulator is shut down. pwm control scheme pulling the sync pin low (<0.4v) forces the converter into pwm mode in the next switching cycle regardless of output current. each of the channels of the ISL8022 employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting shown in the ?block diagram? on page 3. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amp lifier csa1 (or csa2 on channel 2). the gain for the current sensing circuit is typically 0.32v/a. the contro l reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa1 (or csa2) an d the compensation slope (0.9v/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. fi gure 43 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier csa_ output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage control loop. the feedback signal comes from the v fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately shortly. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 250k rc network. the maximum eamp voltage output is precisely clamped to 1.8v. skip mode pulling the sync pin high (> 1.5v) enable the converter into pfm mode at low load. the ISL8022 enters a pulse- skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 44 illustrates the skip-mode operation. a zero-cross sensing circuit shown in block diagram monitors the n-mosfet current for zero crossing. when 16 consecutive cycles of the n-mosfet crossing zero are detected, the regulator enters the skip mode. during the 16 detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in the ?block diagram? on page 3. each pulse cycle is still synchronized by the pwm clock. the p-mosfet is turned on at the clock and turned off when its current reaches the threshold of 600ma. as th e average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% above the nominal voltage, the p-mosfet is turned off immediately. then the inductor current is fully discharged to zero and stays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be turned on again at the clock, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. synchronization control the frequency of operation can be synchronized up to 8mhz by an external signal applied to the sync pin. the 1st falling edge on the sync tr iggered the rising edge of the pwm on pulse of channel 1. the 2nd falling edge of the sync triggers the rising edge of the pwm on pulse of the channel 2. this process alternates indefinitely allowing 180 output phase operation between the two channels.the internal frequency will take control when the divided external sync is lower than 2.25mhz. the falling edge on the sync triggers the rising edge of the pwm on pulse. figure 43. pwm operation waveforms v eamp v csa duty cycle i l v out
ISL8022 15 fn7650.0 june 9, 2010 positive and negative overcurrent protection csa1 and csa2 are used to monitor output 1 and output 2 channels respectively. the overcurrent protection is realized by monitoring the csa_ output with the ocp threshold logic, as sh own in the ?block diagram? on page 3. the current sensing circuit has a gain of 0.32v/a, from the p-mosfet current to the csa_ output. when the csa_ output reaches the threshold of 1.25v for channel 1 and 1.1v for channel 2 , the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfets. upon detection of an overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from low to high. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are seventeen sequential oc fault detections, the regulator will be shut down under an overcurrent fault condition. an overcurrent fault condition will result with the regulator attempting to re start in a hiccup mode with the delay between restarts being 4 soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset and soft-sta rt is attempted again. if the overcurrent condition goes away prior to the oc fault counter reaching a count of four, the overcurrent condition flag will set back to low. if the event when inductor current reaches -1.6a, the part enters negative overcurrent protection. at this point, all switching stops and the part enters tri-state mode while the pull-down fet is discharging the output until it reaches normal regulation voltage, then the ic restarts switching. pg the power-good signal (pg), monitors both of the output channels. when powering up, the open-collector power-on-reset output holds low for about 1ms after v o1 and v o2 reaches the preset voltages. the pg output also serves as a 1ms delayed power-good signal. if one of the outputs is disabled, then pg only monitors the active channels. there is an internal 1m pull-up resistor. uvlo when the input voltage is below the undervoltage lock-out (uvlo) threshold, the regulator is disabled. enable the enable (en1, en2) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and the soft start-up begins. soft start-up the soft start-up eliminates the inrush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. in forced pwm mode, the ic will continue to start-up in pfm mode to support pre-biased load applications. discharge mode (soft-stop) when a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to gnd through an internal 100 switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 100m and the on-resistance for the n-mosfet is typical 90m . 100% duty cycle the ISL8022 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL8022 can no longer maintain figure 44. skip mode operation waveforms clock i l v out nominal +1.5% nominal pfm current limit load current 0 16 cycles pwm pfm
ISL8022 16 fn7650.0 june 9, 2010 the regulation at the output, the regulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shutdown the ISL8022 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +130c, the ISL8022 resumes operation by stepping through a soft start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL8022 typically uses a 1.2h output inductor. higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed as in equation 1: the inductor?s saturation current rating needs to be at least larger than the peak current. the ISL8022 protects the typical peak current 3.2a/2.8a. the saturation current needs to be over 3.6a for maximum output current application. ISL8022 uses internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values are shown in table 1 for the ISL8022 on page 2. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to ?typical applications? on page 2 figure 1. the output voltage programming resistor, r 2 (or r 5 in channel 2), will depend on th e desired output voltage of the regulator. the value for the feedback resistor is typically between 0 and 750k . let r 3 = 100k , then r 2 will be as shown in equation 2: if the output voltage desired is 0.6v, then r 3 is left unpopulated and short r 2 . for better performance, add 10pf in parallel to r 2 . input capacitor selection the main functions for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. one 10f x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection per channel. an optional input inductor can be used before the ceramic capacitor to limit switching noise. it is recommended to limit the inductance less than 0.15h. pcb layout recommendation the pcb layout is a very impo rtant converter design step to make sure the designed converter works well. refer to ISL8022 design procedure for suggestions. for ISL8022, the power loop is composed of the output inductor l?s, the output capacitor c out1 and c out2 , the lx?s pins, and the gnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. the switching node of the converter, the lx_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed to vin pin as close as possible and the ground of input and output capacitors should be connected as close as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) r 2 r 3 v out v fb --------------- - 1 ? ?? ?? ?? = (eq. 2)
ISL8022 17 fn7650.0 june 9, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL8022 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 6/9/10 fn7650.0 initial release.
ISL8022 18 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7650.0 june 9, 2010 for additional products, see www.intersil.com/product_tree dual flat no-lead plastic package (dfn) c // l c e terminal tip for even terminal/side nx (b) section "c-c" 5 (a1) bottom view a 6 area index c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k l l12.4x3 12 lead dual flat no-lead plastic package (compliant to jedec mo-229-vged-4 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.23 0.30 5,8 d 4.00 bsc - d2 3.15 3.30 3.40 7,8 e 3.00 bsc - e2 1.55 1.70 1.80 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n122 nd 6 3 rev. 1 2/05 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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